Method and apparatus for repairing defective columns of memory cells

ABSTRACT

A pair of coupling transistors are connected in series with isolation transistors in each of a plurality of column node circuits coupled to first and second arrays of memory cells arranged in rows and columns. The coupling transistors for the complimentary digit lines in each column node circuit are rendered non-conductive in the event memory cells connected to the coupling transistors through digit lines of the first and second array are defective. As a result, defective memory cells in the first and second arrays are isolated from sense amplifiers in the column node circuits so that the sense amplifiers cannot affect non-defective memory cells.

TECHNICAL FIELD

[0001] The present invention relates to memory devices, particularlydynamic random access memory devices, and, more particularly, to amethod and apparatus for preventing defective columns of memory cellsfrom rendering the entire memory device defective.

BACKGROUND OF THE INVENTION

[0002] A conventional memory device is illustrated in FIG. 1. The memorydevice is a synchronous dynamic random access memory (“SDRAM”) 10 thatincludes an address register 12 adapted to receive row addresses andcolumn addresses through an address bus 14. The address bus 14 isgenerally coupled to a memory controller (not shown in FIG. 1).Typically, a row address is initially received by the address register12 and applied to a row address multiplexer 18. The row addressmultiplexer 18 couples the row address to a number of componentsassociated with either of two memory bank arrays 20 and 22 dependingupon the state of a bank address bit forming part of the row address.The arrays 20 and 22 are comprised of memory cells arranged in rows andcolumns. Associated with each of the arrays 20 and 22 is a respectiverow address latch 26, which stores the row address, and a row decoder28, which applies various signals to its respective array 20 or 22 as afunction of the stored row address. The row address multiplexer 18 alsocouples row addresses to the row address latches 26 for the purpose ofrefreshing the memory cells in the arrays 20 and 22. The row addressesare generated for refresh purposes by a refresh counter 30 that iscontrolled by a refresh controller 32.

[0003] After the row address has been applied to the address register 12and stored in one of the row address latches 26, a column address isapplied to the address register 12. The address register 12 couples thecolumn address to a column address latch 40. Depending on the operatingmode of the SDRAM 10, the column address is either coupled through aburst counter 42 to a column address buffer 44, or to the burst counter42, which applies a sequence of column addresses to the column addressbuffer 44 starting at the column address output by the address register12. In either case, the column address buffer 44 applies a columnaddress to a column decoder 48, which applies various column signals torespective sense amplifiers in associated column circuits 50 for thearrays 20 and 22.

[0004] Data to be read from one of the arrays 20 or 22 are coupled fromthe arrays 20 or 22, respectively, to a data bus 58 through the columncircuit 50, and a read data path that includes a data output register56. Data to be written to one of the arrays 20 or 22 are coupled fromthe data bus 58 through a write data path, including a data inputregister 60, to one of the column circuits 50 where they are transferredto one of the arrays 20 or 22, respectively. A mask register 64 may beused to selectively alter the flow of data into and out of the columncircuits 50 by, for example, selectively masking data to be read fromthe arrays 20 and 22.

[0005] The above-described operation of the SDRAM 10 is controlled by acommand decoder 68 responsive to high level command signals received ona control bus 70. These high level command signals, which are typicallygenerated by the memory controller, are a clock enable signal CKE*, aclock signal CLK, a chip select signal CS*, a write enable signal WE*, arow address strobe signal RAS*, and a column address strobe signal CAS*,where the “*” designates the signal as active low. The command decoder68 generates a sequence of command signals responsive to the high levelcommand signals to carry out a function (e.g., a read or a write)designated by each of the high level command signals. These commandsignals, and the manner in which they accomplish their respectivefunctions, are conventional. Therefore, in the interest of brevity, afurther explanation of these control signals will be omitted.

[0006] A portion of the column circuits 50 of FIG. 1 is shown in greaterdetail in FIG. 2. The column circuit 50 is shown connected to a pair ofarrays 100, 102, which may be subarrays in either of the arrays 20, 22shown in FIG. 1. Alternately, a single column circuit 50 containing thecircuitry shown in FIG. 2 may be used to access both of the arrays 20,22 shown in FIG. 1. The column circuit 50 includes a plurality of columnnode circuits 110 a-n in addition to a redundant column node circuit112. All of these column node circuits 110, 112 are identical, and, inthe interest of clarity and brevity, the internal components of only onecolumn node circuit 110 a is shown in FIG. 2.

[0007] The column node circuit 10 a interfaces with two columns ofmemory cells using two pairs of complementary digit lines D₀, D₀* andD₁, D₁*, respectively. However, it will be understood that the columnnode circuit 110 a may contain fewer or greater numbers of complimentarydigit line pairs. In the interest of brevity, the digit lines D₀, D₀*and D₁, D₁* in the column node circuit 110 as well as in the othercolumn node circuits 110 b-n, 112 will sometimes be referred to assimply D and D*. Each digit line pair D, D* has coupled therebetween anegative sense amplifier 120, a positive sense amplifier 122, anequilibration circuit 124, and an I/O circuit 126.

[0008] The equilibration circuit 124 is controlled by a prechargecontrol circuit 130 that may be part of the row decoders 28 (FIG. 1) tocouple the digit lines D, D* to each other and to an equilibrationvoltage, which typically has a magnitude equal to one-half the magnitudeof a supply voltage. The negative sense amplifier 120 and the positivesense amplifier 122 normally receive respective power signals, typicallyground potential and either the supply voltage or a pumped voltagehaving a magnitude that is slightly greater than the magnitude of thesupply voltage, respectively. After the digit lines D, D* have beenequilibrated by the equilibration circuit 124, the sense amplifiers 120,122 detect a voltage imbalance in the digit lines D, D* during a readaccess of memory cells in the arrays 100, 102. The sense amplifiers 120,122 then drive the digit lines D, D* in the direction of the imbalanceuntil one of the digit lines is at the supply voltage and the other ofthe digit lines is at ground potential.

[0009] Once the sense amplifiers 120, 122 have driven the digit lines D,D* to voltages indicative of the data read from a memory cell in therespective column, the digit lines D, D* are coupled to respective I/Olines I/OA, I/OB* by the I/O circuit 126. As is a well understood in theart, in a read memory access the signals from the digit lines arecoupled to a DC sense amplifier (not shown), which applies acorresponding data signal to the data bus of the memory device. Theother digit lines D₁, D₁* in the column node circuit 110 a are similarlycoupled to a respective pair of I/O lines I/OB, I/OB* by a respectiveI/O circuit 126.

[0010] In a write memory access, the I/O lines are driven by respectivewrite drivers (not shown), and are coupled to the digit lines D, D* bythe I/O circuit 126.

[0011] The column node circuit 110 a receives a SEL_R signal from arespective inverter 114 to cause it to couple its digit lines D, D* tothe I/O lines I/O, I/O*, respectively. Similarly, the column nodecircuit 110 b receives a SEL_R+1 signal to couple its digit lines to thesame I/O lines, and the column node circuit 11 On receives a SEL_R+Nsignal to couple its digit lines to the same I/O lines. Since the SELsignals select various columns of memory cells in the arrays 100, 102,they are normally generated by the column decoder 48 (FIG. 1).

[0012] The I/O circuits 126 in the redundant column node circuit 112 arelikewise coupled to the same I/O lines by a select SEL_RED signal, butthe SEL_RED signal is generated by a redundant column control circuit144. The redundant column control circuit 144 may be part of the columndecoder 48 (FIG. 1).

[0013] As mentioned above, the column node circuits 110 a-n, 112 arecoupled to both arrays 110, 102. However, the column node circuitscannot receive signals indicative of read data from both arrays 100, 102at the same time. For this reason, isolation transistors 150, 152 arecoupled between each digit line D, D* of the column node circuit andcorresponding digit lines D, D*, respectively, of the arrays 100, 102.All of the isolation transistors 150 coupled to the array 100 are turnedON by a common ISO_LEFT signal, and all of the isolation transistors 152coupled to the array 102 are turned ON by a common ISO_RIGHT signal.Since the arrays 100, 102 contain rows of memory cells corresponding todifferent row addresses, the ISO_LEFT and ISO-RIGHT signals aretypically generated by the row decoders 28 (FIG. 1).

[0014] Although the manufacturing yield of memory devices is very good,the large number of transistors, signal paths, and other components,such as capacitors, contained in memory devices creates a significantstatistical probability that a memory device will contain at least onedefective transistor, signal path or other component. For this reason,memory devices typically incorporate rows and columns of redundantmemory cells. If a row or column of memory cells is found to bedefective during testing, either before or after packaging the memorydevice, the memory device can be programmed to substitute a redundantrow of memory cells for the defective row, or a redundant column ofmemory cells for the defective column. The redundant column node circuit112 is provided to interface with redundant columns of memory cells inthe arrays 100, 102. The redundant column node circuit 112 interfaceswith two columns of memory cells, so that two redundant columns aresubstituted whenever a single defective column is found during testing.However, it will be understood that redundant columns can be substitutedon a column-by-column basis, or that redundant columns can besubstituted in groups larger than two. The number of digit lines D, D*in the redundant column node circuit 112 can be adjusted as desired tomatch the number of redundant columns that are substituted.

[0015] Redundant columns of memory cells markedly improve themanufacturing yield of memory devices. However, there are some defectsthat can occur that cannot be repaired by substituting a redundantcolumn. For example, with reference to FIG. 3, a portion of the arrays100, 102 includes access transistors 160 coupled between respectivedigit lines D, D* and a respective storage capacitor 162. Each accesstransistor 160 selectively couples a digit line D or D* to one plate ofthe storage capacitor 162. The other plate of the storage capacitor is a“cell plate” that is typically coupled to a voltage having a magnitudeof one-half of the supply voltage. In operation, the storage capacitors162 store voltages indicative of either a logic “0” or a logic “1”.

[0016] The cell plate of each capacitor 162 is typically common to allof the storage capacitors 162. As a result of manufacturing defects, oneof the digit lines D or D* may be shorted to the cell plate eitherdirectly (the usual failure mode) or through a shorted storage capacitor162. During testing of the memory device, this defect will be detected,and a redundant column of memory cells will be substituted for thedefective column. However, the sense amplifiers 120, 122 in the columnnode circuit 110 for the defective column normally continue to receivethe NLAT and PSENSE signals from the row decoder 28. The senseamplifiers 120, 122 can thus couple the cell plate to either the supplyvoltage or ground potential thereby rendering the remainder of thememory cells defective.

[0017] Although this problem has been recognized in the past, none ofthe approaches that have been developed to deal with this problem areentirely satisfactory. One approach has been to selectively decouple theNLAT and PSENSE signals from the column node circuit 110 for thedefective column of memory cells. Although this approach does prevent ashorted storage capacitor from rendering the remaining cells defective,it does so at great expense. The transistors that are used toselectively couple the NLAT and PSENSE signals to the column nodecircuits 110 must be physically very large to provide a sufficiently lowimpedance path to drive the sense amplifiers 120, 122 so that they canrespond with sufficient speed. Driving the sense amplifiers 120, 122through a relatively high impedance markedly slows the ability of thesense amplifiers 120, 122 to sense voltages on the digit lines D, D*,thereby reducing the access time of the memory device. The amount ofsurface area on a semiconductor die consumed by adding a relativelylarge transistor to each negative sense amplifier 120 and a relativelylarge transistor to each positive sense amplifier 122 is significantbecause of the large number of the sense amplifiers 120, 122 in atypical memory device.

[0018] Another problem with providing transistors to selectively couplethe sense amplifiers 120, 122 to the row decoder 28 is the difficulty ofrouting signal lines in the memory device. More particularly, it wouldbe necessary to supply each column node circuit 110 with two additionalsignal lines coupled to the gates of the transistors. However, it wouldbe difficult to route this many signal lines to the column node circuits110.

[0019] Another approach to preventing defective columns of memory cellsfrom affecting other memory cells has been to place a laser fuse betweeneach column node circuit 110 and the digit lines D, D* of the arrays100, 102 to which they are connected. When a column of memory cells isfound to be defective during testing, a redundant column of memory cellsis substituted for the detective column, and the laser fuse coupling ofthe defective column to its column node circuit 110 is severed. Whilethis approach has been satisfactory in the past, it is becoming less sobecause the minimum laser pitch has not kept up with decreases in digitline pitch. Furthermore, while this approach has been satisfactory forrepairing defects found before the memory device has been packaged, itcannot be used for repairing post-packaging defects.

[0020] Although these problems have been explained with reference to theSDRAM 10 shown in FIG. 1, it will be understood that the same problemsexist with other dynamic random access memories (“DRAMs”) includingasynchronous DRAMs and packetized DRAMs, such as synchronous link DRAMs(“SLDRAMs”) and RAMBUS DRAMs (“RDRAMs”).

[0021] There is therefore a need for a method and apparatus that can beused to repair post-packaging defects in a manner that preventsdefective memory cells in a column from affecting other memory cells andwhich does not unduly increase the cost of memory devices.

SUMMARY OF THE INVENTION

[0022] A method and apparatus for repairing defective columns of memorycells in a memory device does so in a manner that prevents the defectivememory cells from adversely affecting non-defective memory cells. Inaccordance with one aspect of the invention, a plurality of column nodecircuits are provided, each of which includes at least one pair ofcomplimentary digit lines. Each of the column node circuits alsoincludes a sense amplifier, an equilibration circuit, and aninput/output circuit, each of which is coupled between a respective pairof the complimentary digit lines of the column node circuit. A firstpair of coupling switches selectively couples each pair of complimentarydigit lines in each column node circuit to a pair of complimentary digitlines for a respective column in a first array. A second pair ofcoupling switches may optionally be provided to selectively couple eachpair of complimentary digit lines in each column node circuit to a pairof complimentary digit lines for a respective column in a second array.The coupling switches each have a conductive state determined by arespective column node disable signal, which is generated by a redundantcolumn control circuit. The redundant column control circuit generatesthe column node disable signals so that the first and second couplingswitches coupled to the respective column node circuits arenonconductive responsive to a redundant column of memory cells beingsubstituted for the column of memory cells to which the column nodecircuit is coupled.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a block diagram of a conventional SDRAM.

[0024]FIG. 2 is a block diagram and schematic diagram of a portion ofcolumn circuit used in the SDRAM of FIG. 2.

[0025]FIG. 3 is a schematic illustrating a portion of memory arrays usedin the SDRAM of FIG. 2, which interface with the circuitry shown in FIG.2.

[0026]FIG. 4 is a block diagram and schematic diagram of one embodimentof circuitry according to the invention that may be used in the SDRAM ofFIG. 2 in place of the column circuitry shown in FIG. 2.

[0027]FIGS. 5A and 5B are schematics illustrating various embodiments ofcontrol circuitry that may be used in the column circuitry of FIG. 4.

[0028]FIG. 6 is a block diagram of a computer system including the SDRAMof FIG. 1 containing the column circuitry of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

[0029]FIG. 4 illustrated column circuitry according to one embodiment ofthe invention that can be used in the column circuit 50. The circuitryshown in FIG. 4 uses substantially the same column node circuits 110′used in the prior art column node circuits 110 of FIG. 2. Therefore, inthe interest of brevity and clarity, identical components have beenprovided with the same reference numerals, and their operation will notbe repeated.

[0030] With reference to FIG. 4, each of the column node circuits 110′,except for the redundant column node circuit 112, includes a firstcoupling transistor 170 coupling each of its digit lines D, D* to thefirst array 100, and a second coupling transistor 172 coupling each ofits digit lines D, D* to the second array 102. All of the couplingtransistors 170, 172 have their gates connected to each other and to arespective inverter 176. A separate inverter is provided for each of thecolumn node circuits 110′. Power terminals of the inverter 176 areconnected to ground and to a pumped voltage Vccp, respectively, so thatthe inverter 176 outputs one of these two voltages. Each of theinverters 176 is driven by respective control circuitry 178. As shown inFIG. 5A, the control circuitry 178 may be simply a laser fuse 180 biasedhigh by through a resistor 180, or, as shown in FIG. 5B, the controlcircuitry 178 may be an anti-fuse 184 that is also biased high through aresistor 182. The use of an anti-fuse 182 allows both pre-packaging andpost-packaging repairs, while the use of a laser fuse 180 is limited topre-packaging repairs. Alternatively, the control circuitry 178 may beappropriate circuitry (not shown) that interfaces with the redundantcolumn control circuit 144. For example, if a column is defective, itsassociated control circuitry 178 may be programmed to compare its columnaddress with each column address received by the memory device. In theevent of a match, the control circuitry 178 may output an appropriatesignal to the respective inverter 176.

[0031] In operation, the control circuitry 178 normally outputs a lowthereby causing the inverter 176 to output a voltage of Vccp. The Vccpvoltage renders the coupling transistors 170, 172 conductive so that thecolumn node circuit 110′ continues to interface with the arrays 100,102. However, in the event the column of memory for a column nodecircuit 110′ is defective, the control circuitry 178 outputs a highthereby causing the inverter 176 to output a low. The low applied to therespective gates of the coupling transistors 170, 172 renders thetransistors 170, 172 non-conductive, thereby isolating the column nodecircuit 110′ from the digit lines in the arrays 100, 102. As a result,the digit lines D, D* in the arrays 100, 102 are decoupled from thesense amplifiers 120, 122 so that a short in a storage capacitor coupledto a digit line D, D* does not allow the sense amplifiers 120, 122 todrive the cell plate to ground or the supply voltage.

[0032] If a laser fuse 180 (FIG. 5A) is used in the control circuitry178, the laser fuse is left unblown in the event the column of memorywith which it is associated is not defective. The control circuitry 178then applies a low to its inverter 176 so that the inverter outputs avoltage of Vccp. If the column is defective, the output of the controlcircuitry 178 is pulled high through the pull-up resistor 182, therebycausing the inverter 176 to output a low that turns off the couplingtransistors 170, 172.

[0033] In a similar manner, if an anti-fuse 184 (FIG. 5B) is used in thecontrol circuitry 178, the anti-fuse 184 is blown if the column ofmemory with which it is associated is not defective. If the column isdefective, the anti-fuse 184 is left unblown, thereby allowing theoutput of the control circuitry 178 to be pulled high through thepull-up resistor 182.

[0034] In the embodiment of FIG. 4, the coupling transistors 170 coupledto the array 100 are operated in common with the coupling transistors172 coupled to the array 102. However, it will be understood thatseparate control signals may be applied to the transistors 170, 172,respectively. Using this arrangement, a column node circuit 110′ may beisolated from an array 100, 102 containing a defective column of memorycells and continue to interface with the same column of memory cells inthe other array. However, the amount and complexity of circuitry neededto provide separate control signals for the transistors 170, 172 mayvery well outweigh the advantages of being able to access a column ofone array 100 or 102 when the corresponding column of the other array102 or 100 is defective.

[0035] The routing of the signal lines to the coupling transistors 170,172 in the embodiment of the invention shown in FIG. 4 is expected to befairly routine because the signal lines can be routed in parallel withthe signal lines coupling the inverters 114 to the I/0 circuits 126.Moreover, the coupling transistors 170, 172, as well as the circuitrydriving those transistors, can be relatively small since they do notneed to couple a great deal of power. As a result, the circuitry forselectively decoupling the column node circuits 110′ from the arrays100, 102 uses relatively little surface area on the semiconductor diecontaining the memory device.

[0036] In an alternative embodiment, appropriate circuitry (not shown)is used to control the operation of the isolation transistors 150, 152so all of the isolation transistors 150, 152 are non-conductive in theevent a column of memory cells to which they are connected is defective.In addition to controlling the left isolation transistors 150 and theright isolation transistors 152 in all of the column node circuits 110′in two separate groups, the isolation transistors 150, 152 in eachindividual column node circuit 110′ are also controlled on a columnnode-by-column node basis. However, the amount and complexity ofcircuitry that may be required to control the isolation transistors 150,152 so that they perform both their original isolation function and thefunction of isolating column node circuits 110′ from defective columnsof memory cells may outweigh the value of eliminating the couplingtransistors 170, 172 and their associated control circuitry.

[0037]FIG. 6 is a block diagram illustrating a computer system 200including the SDRAM 10′ of FIG. 1 containing the column circuitry ofFIG. 4. The computer system 200 includes a processor 202 for performingvarious computing functions, such as executing specific software toperform specific calculations or tasks. The processor 202 includes aprocessor bus 204 that normally includes an address bus 206, a controlbus 208, and a data bus 210. In addition, the computer system 200includes one or more input devices 214, such as a keyboard or a mouse,coupled to the processor 202 to allow an operator to interface with thecomputer system 200. Typically, the computer system 200 also includesone or more output devices 216 coupled to the processor 202, such outputdevices typically being a printer or a video terminal. One or more datastorage devices 218 are also typically coupled to the processor 202 tostore data or retrieve data from external storage media (not shown).Examples of typical storage devices 218 include hard and floppy disks,tape cassettes, and compact disk read-only memories (CD-ROMs). Theprocessor 202 is also typically coupled to cache memory 226, which isusually static random access memory (“SRAM”) and to the SDRAM 10′through a memory controller 230. The memory controller 230 normallyincludes an address bus coupled to the address bus 14 (FIG. 1) and acontrol bus coupled to the control bus 70. The data bus 58 of the SDRAM10′ is coupled to the data bus 210 of the processor 202, either directlyor through the memory controller 230.

[0038] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. For example, although thedisclosed embodiment of the invention has been described as beingcoupled between two arrays of memory cells, it will be understood thatit may be coupled to a single array of memory cells. Further, althoughthe disclosed embodiment has been described for use in a SDRAM, it willbe understood that it may be used in any present or future developedDRAM, including asynchronous DRAMs and packetized DRAMs, such assynchronous link DRAMs (“SLDRAMs”) and RAMBUS DRAMs (“RDRAMs”).Accordingly, the invention is not limited except as by the appendedclaims.

1. A memory device, comprising a first array of memory cells arranged inrows and columns, the first array including at least one redundantcolumn of memory cells; a control circuit structured to provide controlsignals for controlling the operation of the memory device responsive tocommand signals received by the memory device; a data path circuitstructured to couple data between the first array and an externallyaccessible data bus, the data path circuit including at least one pairof complimentary input/output lines; a row address decoder decoding rowaddresses received by the memory device and activating a row of memorycells corresponding to the row address in the first array; a pluralityof column node circuits each including at least one pair ofcomplimentary digit lines, each of the column node circuits comprising:a sense amplifier coupled between each pair of the complimentary digitlines of the column node circuit; an equilibration circuit coupledbetween each pair of the complimentary digit lines of the column nodecircuit; and an input/output circuit coupled to each pair of thecomplimentary digit lines of the column node circuit, the input/outputcircuit being structured to couple each pair of complimentary digitlines of the column node circuit to a respective pair of complimentaryinput/output lines responsive to a column enable signal; a columnaddress decoder decoding column addresses received by the memory deviceand to generate a plurality of the column enable signals, the columnaddress decoder generating at least one of the column enable signalsresponsive to each of the column addresses; a pair of first couplingswitches selectively coupling each pair of complimentary digit lines ineach column node circuit to a pair of complimentary digit lines for arespective column in the first array, the first coupling switches havinga conductive state determined by a respective column node disablesignal; a second pair of coupling switches selectively coupling eachpair of complimentary digit lines in each column node circuit to a pairof complimentary digit lines for a respective column in the secondarray, the coupling switches having a conductive state determined by therespective column node disable signal; and a redundant column controlcircuit applying a respective column node disable signal to the firstcoupling switches coupled to each of the column node circuits, each ofthe redundant column disable signals causing the first coupling switchescoupled to the respective column node circuits to be non-conductiveresponsive to a redundant column of memory cells being substituted forthe column of memory cells to which the column node circuit is coupled.2. The memory device of claim 1 , further comprising a second array ofmemory cells arranged in rows and columns, the second array including atleast one redundant column of memory cells, the second array beingcoupled to the data path circuit to couple data to and from the secondarray, and to the row address decoder to activate a row of memory cellsin the second array, a pair of second coupling switches selectivelycoupling each pair of complimentary digit lines in each column nodecircuit to a pair of complimentary digit lines for a respective columnin the second array, the second coupling switches having a conductivestate determined by a respective column node disable signal, the secondcoupling switches being coupled to the redundant column control circuit,the redundant column control circuit applying a column node disablesignal to the second coupling switches coupled to each of the columnnode circuits, the redundant column disable signal causing the secondcoupling switches coupled to the respective column node circuits to benon-conductive responsive to a redundant column of memory cells beingsubstituted for the column of memory cells to which the column nodecircuit is coupled.
 3. The memory device of claim 2 wherein each of thecolumn node circuits further comprises an isolation transistor coupledbetween each of the first and second coupling switches and a respectivedigit line of the column node circuit, and wherein the memory devicefurther comprises an isolation control circuit coupled to the first andsecond coupling switches of all of the column node circuits, theisolation control circuit generating isolation control signals thatcause either the first coupling switches or the second couplingswitches, but not both, to be conductive.
 4. The memory device of claim3 wherein the isolation transistors and the coupling switches areseparate components from each other.
 5. The memory device of claim 2wherein each of the column node circuits include a plurality of pairs ofcomplimentary digit lines each of which is coupled to a pair ofcomplimentary digit lines in the first array by one of the pairs offirst coupling switches and to a pair of complimentary digit lines inthe second array by one of the pairs of second coupling switches.
 6. Thememory device of claim 1 wherein each of the first coupling switchescomprise a field effect transistor.
 7. The memory device of claim 1wherein each of the redundant column control circuits comprises arespective programmable impedance element having a conductive state anda non-conductive state.
 8. The memory device of claim 7 wherein each ofthe programmable impedance elements comprises a laser fuse.
 9. Thememory device of claim 7 wherein each of the programmable impedanceelements comprises an anti-fuse.
 10. The memory device of claim 1wherein the memory device comprises a dynamic random access memory. 11.The memory device of claim 10 wherein the memory device comprises asynchronous dynamic random access memory.
 12. The memory device of claim1 wherein the column enable signal coupled to each of the column nodecircuits and the redundant column disable signal applied to the firstcoupling switches for the associated column node circuit are coupledthrough respective conductors that are positioned in parallel with eachother.
 13. A column circuit adapted for coupling to a first array ofmemory cells arranged in rows and columns, the column circuitcomprising: a plurality of column node circuits each including at leastone pair of complimentary digit lines, each of the column node circuitscomprising: a sense amplifier coupled between each pair of thecomplimentary digit lines of the column node circuit; an equilibrationcircuit coupled between each pair of the complimentary digit lines ofthe column node circuit; and an input/output circuit coupled to eachpair of the complimentary digit lines of the column node circuit, theinput/output circuit being structured to couple the pair ofcomplimentary digit lines of the column node circuit to a pair ofcomplimentary input/output lines, respectively, responsive to a columnenable signal; a pair of first coupling switches selectively couplingeach pair of the complimentary digit lines in each column node circuitto respective pairs of complimentary digit lines in the first array, theswitches having a conductive state determined by a respective columnnode disable signal; and a redundant column control circuit applyingrespective column node disable signals to the first coupling switches ineach of the column node circuit, each of the redundant column disablesignals causing the first coupling switches coupled to the respectivecolumn node circuits to be non-conductive responsive to a redundantcolumn of memory cells being substituted for the column of memory cellsto which the column node circuit is coupled.
 14. The column circuit ofclaim 13 wherein the column circuit is coupled to a second array ofmemory cells arranged in rows and columns, the column circuit furthercomprising a pair of second coupling switches coupled to each pair ofthe complimentary digit lines in each column node circuit to respectivepairs of complimentary digit lines in the second array, the switcheshaving a conductive state determined by a respective column node disablesignal, the second coupling switches being coupled to the redundantcolumn control circuit, the redundant column control circuit applying acolumn node disable signal to the second coupling switches coupled toeach of the column node circuits, the redundant column disable signalcausing the second coupling switches coupled to the respective columnnode circuits to be nonconductive responsive to a redundant column ofmemory cells being substituted for the column of memory cells to whichthe column node circuit is coupled.
 15. The column circuit of claim 14wherein each of the column node circuits further comprises an isolationtransistor coupled between each of the first and second couplingswitches and a respective digit line of the column node circuit.
 16. Thecolumn circuit of claim 15 wherein the isolation transistors and thefirst and second coupling switches are separate components from eachother.
 17. The column circuit of claim 14 wherein each of the columnnode circuits include a plurality of pairs of complimentary digit lineseach of which is coupled to a pair of complimentary digit lines in thefirst array by one of the pairs of first coupling switches and to a pairof complimentary digit lines in the second array by one of the pairs ofsecond coupling switches.
 18. The column circuit of claim 13 whereineach of the first coupling switches comprise a field effect transistor.19. The column circuit of claim 13 wherein each of the redundant columncontrol circuits comprises a respective programmable impedance elementhaving a conductive state and a non-conductive state.
 20. The columncircuit of claim 19 wherein each of the programmable impedance elementscomprises a laser fuse.
 21. The column circuit of claim 19 wherein eachof the programmable impedance elements comprises an anti-fuse.
 22. Thecolumn circuit of claim 13 wherein the column enable signal coupled toeach of the column node circuits and the redundant column disable signalapplied to the first coupling transistors for the associated column nodecircuit are coupled through respective conductors that are positioned inparallel with each other.
 23. A computer system, comprising: a processorhaving a processor bus; an input device coupled to the processor throughthe processor bus adapted to allow data to be entered into the computersystem; an output device coupled to the processor through the processorbus adapted to allow data to be output from the computer system; and amemory device, comprising a first array of memory cells arranged in rowsand columns, the first array including at least one redundant column ofmemory cells; a control circuit structured to provide control signalsfor controlling the operation of the memory device responsive to commandsignals received by the memory device; a data path circuit structured tocouple data between the first array and an externally accessible databus, the data path circuit including at least one pair of complimentaryinput/output lines; a row address decoder decoding row addressesreceived by the memory device and activating a row of memory cellscorresponding to the row address in the first array; a plurality ofcolumn node circuits each including at least one pair of complimentarydigit lines, each of the column node circuits comprising: a senseamplifier coupled between each pair of the complimentary digit lines ofthe column node circuit; an equilibration circuit coupled between eachpair of the complimentary digit lines of the column node circuit; and aninput/output circuit coupled to each pair of the complimentary digitlines of the column node circuit, the input/output circuit beingstructured to couple each pair of complimentary digit lines of thecolumn node circuit to a respective pair of complimentary input/outputlines responsive to a column enable signal; a column address decoderdecoding column addresses received by the memory device and to generatea plurality of the column enable signals, the column address decodergenerating at least one of the column enable signals responsive to eachof the column addresses; pairs of first coupling switches selectivelycoupling each pair of complimentary digit lines in each column nodecircuit to a pair of complimentary digit lines for a respective columnin the first array, the first coupling switches having a conductivestate determined by a respective column node disable signal; a secondpair of coupling switches selectively coupling each pair ofcomplimentary digit lines in each column node circuit to a pair ofcomplimentary digit lines for a respective column in the second array,the coupling switches having a conductive state determined by therespective column node disable signal; and a redundant column controlcircuit applying a respective column node disable signal to the firstcoupling switches coupled to each of the column node circuits, each ofthe redundant column disable signals causing the first coupling switchescoupled to the respective column node circuits to be nonconductiveresponsive to a redundant column of memory cells being substituted forthe column of memory cells to which the column node circuit is coupled.24. The computer system of claim 23 wherein the memory device furthercomprises: a second array of memory cells arranged in rows and columns,the second array including at least one redundant column of memorycells, the second array being coupled to the data path circuit to coupledata to and from the second array, and to the row address decoder toactivate a row of memory cells in the second array, a pair of secondcoupling switches selectively coupling each pair of complimentary digitlines in each column node circuit to a pair of complimentary digit linesfor a respective column in the second array, the second couplingswitches having a conductive state determined by a respective columnnode disable signal, the second coupling switches being coupled to theredundant column control circuit, the redundant column control circuitapplying a column node disable signal to the second coupling switchescoupled to each of the column node circuits, the redundant columndisable signal causing the second coupling switches coupled to therespective column node circuits to be non-conductive responsive to aredundant column of memory cells being substituted for the column ofmemory cells to which the column node circuit is coupled.
 25. Thecomputer system of claim 24 wherein each of the column node circuitsfurther comprises an isolation transistor coupled between each of thefirst and second coupling switches and a respective digit line of thecolumn node circuit, and wherein the memory device further comprises anisolation control circuit coupled to the first and second couplingswitches of all of the column node circuits, the isolation controlcircuit generating isolation control signals that cause either the firstcoupling switches or the second coupling switches, but not both, to beconductive.
 26. The computer system of claim 24 wherein the isolationtransistors and the coupling switches are separate components from eachother.
 27. The computer system of claim 24 wherein each of the columnnode circuits include a plurality of pairs of complimentary digit lineseach of which is coupled to a pair of complimentary digit lines in thefirst array by a first coupling switch and to a pair of complimentarydigit lines in the second array by a second coupling switch.
 28. Thecomputer system of claim 23 wherein each of the coupling switchescomprise a field effect transistor.
 29. The computer system of claim 23wherein each of the redundant column control circuits comprises arespective programmable impedance element having a conductive state anda non-conductive state.
 30. The computer system of claim 29 wherein eachof the programmable impedance elements comprises a laser fuse.
 31. Thecomputer system of claim 29 wherein each of the programmable impedanceelements comprises an anti-fuse.
 32. The computer system of claim 23wherein the memory device comprises a dynamic random access memory. 33.The computer system of claim 32 wherein the memory device comprises asynchronous dynamic random access memory.
 34. The computer system ofclaim 23 wherein the column enable signal coupled to each of the columnnode circuits and the redundant column disable signal applied to thefirst coupling transistors for the associated column node circuit arecoupled through respective conductors that are positioned in parallelwith each other.
 35. A method of coupling data signals between of aplurality of pairs of complimentary digit lines in a first array ofmemory cells and a plurality of column circuits, the method comprising:coupling the data signals between at least one pair of complimentarydigit lines in each column circuit and corresponding pairs ofcomplimentary digit lines in the first array, in the event the digitlines in the first array are not defective; and isolating the firstarray from a column circuit if any digit lines in the first arraycorresponding to digit lines in the column circuit are defective. 36.The method of claim 35 wherein the data signals are coupled between thecolumn circuits and a plurality of pairs of complimentary digit lines ina second array of memory cells, the method comprising: coupling the datasignals between at least one pair of complimentary digit lines in eachcolumn circuit and corresponding pairs of complimentary digit lines inthe second array in the event the digit lines in the second array arenot defective; and isolating the second array from the column circuit ifany digit lines in the second array corresponding to digit lines in thecolumn circuit are defective.
 37. The method of claim 34 furthercomprising substituting a pair of complimentary digit lines for the pairof complimentary digit lines in the first array that are defective. 38.The method of claim 35 wherein the memory device comprises a dynamicrandom access memory.
 39. The method of claim 38 wherein the memorydevice comprises a synchronous dynamic random access memory.
 40. Themethod of claim 35 wherein each of the column circuits comprises twopairs of complimentary digit lines.